The present invention relates to a multi-processor system capable of executing a lock operation at high speed.
In order for a plurality of processors of a multi-processor system to share data of a main storage (hereinafter represented by MS), it is necessary to provide a lock function to allow one processor to read/write data by inhibiting another processor from accessing the data for a predetermined time period. A technique regarding such a lock function is described, for example, in Japanese Laid-open Publication JP-A-63-259758.
This conventional technique will be described below.
Each individual processor (hereinafter represented by IP) is provided with a buffer storage (hereinafter represented by BS) under store through control and a buffer address array (hereinafter represented by BAA) for storing a directory of the BS. A storage controller (hereinafter represented by SC) is provided with a front address array (hereinafter represented by FAA) for storing a copy of a part of the BAA.
Each entry of the BAA has a reserve bit (hereinafter represented by RSV bit) and a lock bit (hereinafter represented by L bit), and the FAA has a copy of the RSV bits of the BAA.
A lock requesting IP refers to an entry of the BAA corresponding to a lock address. If the RSV bit is "1", the lock requesting IP immediately sets "1" in the L bit to thereafter enter a lock state.
If the RSV bit is not "1", the lock requesting IP sends the lock address to the SC. The SC refers to all RSV bits of the FAA at the corresponding entry. If there is an FAA entry having an RSV bit "1", then the SC issues a cancel request to the IP corresponding to the FAA entry having an RSV bit "1". After the cancel operation is completed, or if there is no FAA entry having an RSV bit "1", the RSV bit in the FAA entry of the lock requesting IP is set to "1". The SC notifies the lock requesting IP of a lock acceptance. The lock requesting IP then sets "1" in the corresponding RSV bit and L bit to thereafter enter a lock state.
Releasing the lock state is realized by setting "0" in the L bit of the BAA.
If one IP is entering a lock state, the RSV bit of a BAA entry of another IP which intends to access the lock address is necessarily "0". Therefore, a request is issued to the SC which in turn issues a cancel request to the locking IP having the RSV bit "1" at the corresponding FAA entry. The locking IP will not respond to this cancel request until it releases the lock state. Therefore, an access to the lock address by the other lock requesting IP will be delayed until the lock state is released.
The conventional technique has realized the lock function by the operation described above.
According to the above-described conventional technique, a copy of a part of the MS is exclusively stored in the BS of each IP. While one IP locks and accesses a block of the MS, an access to the block by another IP is inhibited and delayed until the lock state is released.
The IP sends a request and a request address to the SC for storage of a copy of a block of the MS, whereas the SC returns a lock acceptance to the IP for permission to store the block. Therefore, it is necessary to provide signal lines for the request, the request address, and the lock acceptance, between the SC and each IP.
As the number of the IPs in a multi-processor system increases, the number of signal lines increases proportionally. The number of signal lines is limited, however, by restrictions such as the number of pins of an LSI and the like.
In view of the above problem, in the conventional technique, the control signal lines for the request, the lock acceptance, and the like are provided independently for each IP, whereas a number of address signal lines are made of a bus commonly used by all the IPs.
With the bus for the signal lines of the request address, it is not possible for a plurality of IPs to send request addresses at the same time. It becomes necessary therefore to provide means for arbitrating a bus privilege between IPs.
For the arbitration of a bus privilege, a bus acceptance signal is used for giving a bus privilege to a lock requesting IP from the SC. Addition of the bus acceptance signal makes the control logic somewhat complicated increases the time required for the IP to issue a request. This disadvantage is inherent to a bus and can be permissible. Apart from the above, two functions must be additionally provided. Namely, with the first function, if the SC cannot send back an acceptance immediately after the IP responds to a bus acceptance signal and sends a request address because another IP is locking the block, the lock requesting IP is requested to immediately release the bus privilege, and the SC is allowed to receive another lock request from another IP. With the second function, the SC is allowed to receive a request from the IP while holding the request address sent by another IP. However, if the first function is provided to immediately release a bus privilege and receive another request from another IP if an immediate response of a lock acceptance is not possible, the control logic of the SC becomes very complicated.